1. Field of the Invention
The invention relates to a lock detector circuit for a phase-locked loop comprising at least two counters and a comparator, which receives the counter readings of the two counters. The comparator has a counter reading checking device in which the counter readings are monitored and the phase-locked loop is controlled into the locked state when one of the two counter readings reaches a predetermined final value.
Phase-locked loops (PLL) are used to correct frequency differences between an input signal and a comparison signal. In other words, the phase-locked loop adjusts the frequency of a comparison signal to the frequency of the input signal. The frequency of the comparison signal is either the output frequency of the phase-locked loop directly or it is set in a defined ratio to the output frequency via a divider. The error signal required for the control operation is obtained from the phase difference between the input signal and the comparison signal with the aid of a phase detector.
As long as the frequencies of the input signal and of the comparison signal are far apart, the difference frequency falls outside the passband of the low-pass filter and an error voltage is not produced at the input of the oscillator (VCO) of the phase-locked loop. The oscillator then oscillates at the free-running frequency. The phase-locked loop is not locked in this case.
However, if the frequencies of the input signal and of the output signal come closer to one another, then the situation arises wherein the difference frequency falls within the passband of the low-pass filter. The phase-locked loop is locked in this case. A circuit configuration which detects whether the phase-locked loop is in the locked state is referred to as a lock detector circuit (also: lock detect circuit, lock detection circuit). Such a lock detector circuit generates a binary control signal which, for example, is 0 whenever the phase-locked loop is not locked and which switches to 1 when the phase-locked loop locks.
A generic lock detector circuit for a phase-locked loop is illustrated in FIG. 1. There, a respective input clock signal TA, TB is coupled into a counter ZA, ZB. The first input signal TA may be, for example, the divided-down output signal of the phase-locked loop. The second input signal TB may be the reference signal which is generated by a crystal oscillator, for example.
The counter read signals CA, CB can be picked off at the output of the counters ZA, ZB. The counter readings CA, CB of the two counters ZA, ZB are fed to a comparator V. A lock signal LOCK is available at the output of the comparator V. The counters ZA, ZB can be reset to zero via a reset input RE.
The lock detector circuit LD of FIG. 1 operates as follows:
Assume that the two counters ZA, ZB are negatively edge-triggered. It should be understood, however, that, depending on the specific requirements, they may also be positively edge-triggered. The counters ZA, ZB determine the counter readings CA, CB using the clock frequency of the input signals TA, TB at the input terminals.
If one of the two counters, for example the counter ZA, has reached a predetermined final value, for example 100, then the second counter ZB must likewise reach the predetermined value 100 before the rising edge of the clock signal TA, which is coupled into the first counter ZA, appears. For this case, the comparator V generates at its output a binary control signal LOCK=1, which controls the phase-locked loop into the locked state. The counter readings of the counters ZA, ZB are reset simultaneously via a rest signal RESET.
In the non-locked state, the counter readings CA, CB differ, after one of the two counters ZA, ZB has reached the predetermined value, by more than one clock period, for example. In that case, the comparator outputs a binary control signal LOCK=0, as a result of which the phase-locked loop is set to the non-locked state.
The lock detector circuit of FIG. 1 is conventionally used as a safeguarding circuit for detecting gross frequency differences caused, for example, by a system reset.
Power saving modes are increasingly demanded in integrated circuits, in particular large-scale integrated microprocessors and micro-controllers. Such a power saving mode is the power down mode, for example. In the power down mode, the functional units of the integrated circuit or microprocessor are switched off or greatly slowed down and, consequently, the integrated circuit or the microprocessor is put into an idle state, as it were. In the power down mode, the phase-locked loop, in particular, is switched off. However, it is necessary, at the end of the power down mode, for the lock detector circuit reliably to detect whether the phase-locked loop is locked or not locked.
Such a circuit configuration proves to be problematic, however. Due to the integral summation of the clock signals coupled into the counters ZA, ZB, frequency deviations may remain undiscovered if they are compensated for on average within the counting period given by the predetermined final value of the counters. This is the case particularly when the predetermined final value is chosen to be very large.
If, for example at the start of the predetermined counting period, a change occurs in the frequency of one of the two clock signals that are input, then the phase-locked loop has enough time to react to the irregularity, and possibly compensate for it, before one of the two counters has reached the predetermined final value. However, if the frequency disturbance occurs at the end of the predetermined clock period, the phase-locked loop no longer has time to react to it and compensate for the frequency difference.
This may result in an undesirable state that is referred to as the metastable state: if the control signal of the lock detector circuit is LOCK=0, then the phase-locked loop is actually in the non-locked state. If, however, the control signal is LOCK=1, then the phase-locked loop may be either in the locked or non-locked state.
The counters of the lock detector circuit according to FIG. 1 sum the respective clock signals using the negative edges of the clock signals that are coupled in. The two clock signals that are coupled into the phase-locked loop are set in such a way that in each case one of the clock-signal edges, for example the negative clock-signal edge, correspond to one another. However, the positive clock-signal edge of the PLL clock signal that is coupled in does not usually correspond to the positive clock-signal edge of the reference clock signal, since the duty ratio of the PLL clock signal that is coupled in depends on the clock generator of the user of the external circuitry and the duty ratio of the reference clock signal depends on the PLL factor that is set. Since the sensitivity of the lock detector circuit depends on the position of the positive and negative clock-signal edges relative to one another, it may likewise happen, undesirably, that the phaselocked loop is controlled into the non-locked state even though it is actually locked.